Sina Mohammadi Ali Akbar — Matrikelnummer: 12249534
A signal arriving too late is indistinguishable from a wrong answer.
Voltage transitions in silicon
Pure delay, inertial delay, their limits
Past switching shapes future delay
Fast, trace-aware simulation
A correct value after the clock edge is a failure.
Correct
Too Late
Deadline Missed
Failure
Every instruction ultimately executes as a voltage transition in silicon.
Instructions & algorithms
Physical integrated circuit
NAND, NOR, inverters
Rising & falling transitions
Functional correctness alone is not enough.
Correct Boolean value
Arrives before deadline
Scales to billions of gates — but uses worst-case margins, not real signal history.
No input vectors needed
Worst-case assumptions, not actual traces
Dynamic switching effects not captured
Solves transistor-level equations — the reference for accuracy, but doesn't scale.
Captures transistor-level analog effects
Cost grows rapidly with circuit size
Used to validate other timing models
Trace-aware. Event-driven. No analog equations.
Real signal history
History-aware delay function
Discrete switching events
Predicted waveform
Faster than SPICE. More faithful than STA.
Real gates degrade pulses — fixed-delay models cannot capture this.
Shifted pulse. Glitches unchanged.
Short pulses filtered. Shape ignored.
Amplitude reduced. Threshold shifted.
Delay depends on history — the time since the last transition.
Switching event arrives
Analog charge not fully settled
Time since last transition
Varies with T
Same input. Different delay. The gate remembers.
When two inputs switch close together, delay can change by ~30%.
Switching with separation Δ
Internal currents interact
Can change by ~30%
Same NOR gate. Smaller Δ. Different output delay.
From one NOR gate to full circuit-level symbolic timing.
History-aware single-gate model
Different topology, same framework
Gate with persistent internal memory
Multi-gate timing composition
Full circuit-level verification
Why Digital Timing Simulation Matters